[ADI 上海 2007年度毕业生招聘 /center] College Hire Analog / Mixed Signal Design Engineer (Shanghai)   Job Description : * Support the design of product * Design of analog/mixed signal circuits by using state of the art CMOS proces s technologies   Qualifications: * MS degree in electonics or above * Experience with CMOS design * Solid knowledge in the theory * Good knowledge of solid state technologies * Solid knowledge of English language Mail: Jinghua.Ye@analog.com ------------------------------------------------------------------------------ ---------------------------------------------- ASIC/Digital Design Engineer (Shanghai) Job Description: Need to work on Design SPEC, RTL coding, test environment development functional verification, Timing closure and bench debugging with other team me mbers. Qualification: *MSEE/Above *Strong RTL coding and debugging experience. *Team work spirit. *Familiar with Verilog HDL, *Knowledge of Synopsys design compiler, STA and ASIC design flow. Mail: Rocky.Pan@analog.com ------------------------------------------------------------------------------ ---------------------------------------------- Application/Test Engineer (Shanghai) Job Description: 1、 Responsible for new design Test Architecture and implementation, using the design team. Generate and implement production test programs using techniques such as SCAN, BIST, DAC, and high speed functional testing. Develop DFT methodology. 2、Interface Design teams to define the test architecture and implement it, an d with Test Development Eng. for Test Vector implementation. Work closely with internal and external teams to support pattern validation, c haracterization, silicon debug. Work closely with foundries and assembly/test sites to insure smooth high volu me production. 3、Responsible for achieving sufficient test coverage. Qualification: 1、BSEE required or MS preferred. 2、Must have experience in testing and characterizing of ASICs and Analog Circ uit. 3、Strong understanding & hands on experience with industry standard DFT metho dology/techniques such as JTAG, boundary scan, scan/ATPG/Fault simulation, mem ory BIST & repair, scan compression/BIST. 4、Strong hands on DFT integration/tapeout of large chips with the logic desig n flow, modeling, RTL-implementation & verification, logic synthesis, logic eq uivalent checking, static timing analyses, signal integrity checks & back end support for timing closure. 5、Understanding of CMOS circuit design and analysis. 6、Logic Bist knowledge and analog circuit test are preferable. 7、Working knowledge of ATE equipment like Teradyne FLEX. 8、Solid understand of Design For Test concepts, implementation tools, and imp act on schedules. 9、GOOD English language oral and written communications skills. Mail: Wei.Yao@analog.com