SD/MMC存储卡控制芯片

Features

  SD card standard

System specification SD2.0 compliance.

SPI mode supported

Command class 0,2,4,5,6,7,8,10 supported

CPRM supported

Speed class up to 6

Support host clock up to 50 MHz

Supported bus width: X1, X4

Supported sleep mode 
MMC card standard

System specification MMC4.2 compliance.

SPI mode supported

Command class 0 to 8 supported

Support host clock up to 52 MHz

Supported bus width: X1, X4, X8

Dual voltage MMC supported

Supported sleep mode

  Fastest data transfer rate on the market : Dual-channel mode: 24MB/s for Read, 16MB/s for Write Single-channel mode: 14MB/s for Read, 9MB/s for Write

 On-the-fly ECC built-in Hardware enhances reliability ECC for Binary NAND flash: 4-32 bit/page (1 page = 528 bytes) ECC for MLC NAND flash: 8-32 bit/page ECC for AG-AND flash: 8-32 bit/page

 Hardware & Software Data Protection Technology

Prevent data corruption even if it is powered off or unplugged during data transfer.

NAND, AG-AND & MLC Flash Interface

Supports Samsung & Toshiba NAND flash memories Supports Toshiba & Sandisk MLC flash memories Supports Renesas AG-AND flash memories Supports Infineon / Hynix flash memories Supports ST Microelectronics flash memories Supports Micron / Actrans flash memories Software configuration to support various new flash memories Supports up to 8 flash chips.

 Proprietary 32-bit CISC microprocessor feature

Proprietary 32-bit CISC processor for SD/MMC protocol processing and flash access.

Single cycle instruction period

 Low power dissipation

Operating current 10 mA, suspend current 2 mA

 Leading 0.18um CMOS technology

 48-pin TQFP or QFN package

48-pin CBM3080 supports up to 4 Flash Chips